Table 2-9 Binary Arithmetic Addition Rules

 

Figure 2-1 Half-Adder

Observe from Table 2-9 that we may derive logical expressions for the Sum (S) and carry output (C_O) bits. Namely,     C_O = AB, and . From these two expressions, the implementation of the half-adder function is developed as illustrated in Figure 2-2.

Figure 2-2 Logic Circuit for half-adder

 Full Adder

The second basic category of adder is the full-adder. This combinational circuit performs the arithmetic addition of three input bits. The noticeable difference between the full- and the half-adder is the ability of the former to handle input carries (C_I). The logical symbol for the half-adder is shown in Figure 2-3 and the associated truth table in Table 2-10.

Figure 2-3 Full-Adder

Table 2-10 Full-adder truth table

 

By the very nature of the full adder we know that the two input bits must be added to the carry input bit. Recall that for the half-adder the sum of A and B is the XOR of those two variables,. Similarly, for the three variables A, B and C_I the sum becomes . This is illustrated in Figure 2-4.

Figure 2-4 Logic circuit for

 By examining Table 2-10 observe that the carry output (C_O) is ‘1’ when both the inputs to the first and second XOR gates are ‘1’. Consequently, . Note that the complete logic circuit for the full adder is illustrated in Figure 2-5.

Figure 2-5 Logic Circuit for the full-adder

Figure 2-6 shows how two half-adders can be arranged to form a full adder.

Figure 2-6 Block Diagram of full-adder