SR Flip Flop
Select An Input Value None SET RESET

An SR Flip Flop is an arrangements of logic gates that maintains a stable output even after the inputs are turned off.  This simple flip flop circuit has a set input (S) and a reset input (R). The set input causes the output of 0 (top output) and 1 (bottom output).  The reset input causes the opposite to happen (top = 1, bottom =0).  Once the outputs are established, the wiring of the circuit is maintained until S or R go high, or power is turned of to the circuit.

This is a simple model of how a bit of RAM can be perpetuated.  There are many issues not shown here such as timing inputs and synchronization, but the simplicity of the circuit gives you an idea of how RAM operates.

An SR Flip Flop is an arrangements of logic gates that maintains a stable output even after the inputs are turned off.  This simple flip flop circuit has a set input (S) and a reset input (R). The set input causes the output of 0 (top output) and 1 (bottom output).  The reset input causes the opposite to happen (top = 1, bottom =0).  Once the outputs are established, the wiring of the circuit is maintained until S or R go high, or power is turned of to the circuit.

This is a simple model of how a bit of RAM can be perpetuated.  There are many issues not shown here such as timing inputs and synchronization, but the simplicity of the circuit gives you an idea of how RAM operates.